Semiconductor elements configured with various semiconductor materials (hereinafter also simply referred to as “elements”), such as IC using silicon semiconductor and organic EL elements using organic semiconductors, are usually produced by repeatedly forming a matrix of multiple elements on a wafer substrate, then dicing the substrate into individual elements known as semiconductor chips (also referred to as bare chips).
In the description below, a semiconductor element formed thereon (state prior to dicing) is also referred to as “a semiconductor wafer”, and the state prior to dicing is also referred to as “a wafer state”. Likewise, a diced semiconductor chip is also simply referred to as “a chip”, and the state after dicing is also referred to as “a chip state”.
In addition to a basic semiconductor element structure, various wiring structures are fabricated in the element while in the wafer state, in order to add sophisticated functions and for other purposes. Such wiring structures include, for example, a redistribution layer, conductive path (through hole via) that allow the element-side face and back face to communicate with each other electrically through a wafer substrate, and the like.
As disclosed in JP-A-2000-243754, for example, an aluminum electrode (an electrode pad included in an element as a semiconductor element structure) is formed, after which an insulating layer, a Cu-plated layer and the like are sequentially formed thereon, whereby a redistribution layer is formed.
After being provided with a wiring structure and divided into chips, any element serves as a semiconductor device with a connecting conductor that facilitates connection to, and mounting of, external conductors (external circuits and the like), compared with the original element, which simply has an is electrode exposed.
For example, by providing a redistribution layer, aluminum electrodes of the element and conductors on an external circuit for mounting the element can easily be connected, even if they differ from each other in size or pitch.
Connection terminals can be formed on the back face of a wafer substrate by providing through hole vias that penetrate the wafer substrate in the direction of the substrate thickness.
Through investigations of such wiring layer to be added to a semiconductor element, the present inventors found that there was a room for further improvement in the manufacturing cost relating to the wiring layer, and identified it as a problem to be solved by the present invention.
Accordingly, processing for forming a redistribution layer directly on a semiconductor wafer is painstaking because of the necessity for building a redistribution layer on each semiconductor wafer. The present inventors took note of the fact that there is a room for reducing the manufacturing cost for forming such a redistribution layer, although this had not been deemed a problem. If a redistribution layer formed is found to be of unacceptable quality, and even if the semiconductor wafer obtained is of acceptable quality as a whole, disposal of the semiconductor wafer as well is unavoidable, which increases the manufacturing cost, because the redistribution layer has already been formed monolithically on the semiconductor wafer.
Problems to be solved by the present invention reside in resolving the above-described problem of which the present inventors took note and to provide a manufacturing method that enables a reduction of the manufacturing cost for redistribution layers conferred to semiconductor elements.